 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ispGAL(R)22LV10 In-System Programmable Low Voltage E2CMOS(R) PLD Generic Array LogicTM Features * IN-SYSTEM PROGRAMMABLE -- IEEE 1149.1 Standard TAP Controller Port Programming -- 4-Wire Serial Programming Interface -- Minimum 10,000 Program/Erase Cycles * HIGH PERFORMANCE E2CMOS(R) TECHNOLOGY -- 4 ns Maximum Propagation Delay -- Fmax = 250 MHz -- 3 ns Maximum from Clock Input to Data Output -- UltraMOS(R) Advanced CMOS Technology * 3.3V LOW VOLTAGE 22V10 ARCHITECTURE -- JEDEC-Compatible 3.3V Interface Standard -- 5V Tolerant Inputs and I/O -- I/O Interfaces with Standard 5V TTL Devices * ACTIVE PULL-UPS ON ALL LOGIC INPUT AND I/O PINS * COMPATIBLE WITH STANDARD 22LV10/22V10 DEVICES -- Function/Fuse-Map Compatible with 22LV10/22V10 Devices -- Parametric Compatible with 22LV10 * E2 CELL TECHNOLOGY -- In-System Programmable Logic -- 100% Tested/100% Yields -- High Speed Electrical Erasure (<100ms) -- 20 Year Data Retention * APPLICATIONS INCLUDE: -- DMA Control -- State Machine Control -- High Speed Graphics Processing -- Software-Driven Hardware Configuration * ELECTRONIC SIGNATURE FOR IDENTIFICATION Functional Block Diagram Spe Gra ed de w 4ns Ne I/CLK RESET 8 OLMC I/O/Q I 10 I 12 OLMC I/O/Q I OLMC I/O/Q PROGRAMMABLE AND-ARRAY (132X44) I 14 OLMC I/O/Q I 16 OLMC I/O/Q I 16 OLMC I/O/Q I 14 OLMC I I/O/Q 12 I OLMC I/O/Q I 10 OLMC I/O/Q I TDO TDI TMS TCK PROGRAMMING LOGIC 8 OLMC I/O/Q PRESET Description The ispGAL22LV10 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. The ispGAL22LV10 can interface with both 3.3V and 5V signal levels. The ispGAL22LV10 is fully function/fuse map compatible with the GAL(R)22LV10 and GAL22V10. Further, the ispGAL22LV10 is parametric compatible with the GAL22LV10. The ispGAL22LV10 also shares the same 28-pin PLCC package pin-out as the GAL22LV10. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 10,000 erase/write cycles and data retention in excess of 20 years are specified. Pin Configuration PLCC I/CLK I/O/Q I/O/Q TCK Vcc I I SSOP 4 I I I TMS I I I 11 12 9 7 5 2 28 26 25 I/O/Q I/O/Q ispGAL22LV10 Top View 23 I/O/Q TDO 21 I/O/Q I/O/Q 14 16 19 18 I/O/Q TCK I/CLK I I I I I TMS I I I I I GND 1 28 7 ispGAL 22LV10 22 Top View 14 15 Vcc I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q TDO I/O/Q I/O/Q I/O/Q I/O/Q I/O/Q I TDI Copyright (c) 1999 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. I/O/Q I/O/Q GND TDI I I I LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com December 1999 isp22lv_06 1 Specifications ispGAL22LV10 Ordering Information Commercial Grade Specifications Tpd (ns) 4 5 7.5 10 15 Tsu (ns) 3 3.5 5 7 10 Tco (ns) 3 3.5 5 6.5 8 Icc (mA) 130 130 130 130 130 Ordering # ispGAL22LV10-4LJ ispGAL22LV10-4LK ispGAL22LV10-5LJ ispGAL22LV10-5LK ispGAL22LV10-7LJ ispGAL22LV10-7LK ISPGAL22LV10-10LJ ispGAL22LV10-10LK ispGAL22LV10-15LJ ispGAL22LV10-15LK Package 28-Lead PLCC 28-Lead SSOP 28-Lead PLCC 28-Lead SSOP 28-Lead PLCC 28-Lead SSOP 28-Lead PLCC 28-Lead SSOP 28-Lead PLCC 28-Lead SSOP Industrial Grade Specifications Tpd (ns) 7.5 10 15 Tsu (ns) 5 7 10 Tco (ns) 5 6.5 8 Icc (mA) 160 160 160 Ordering # ispGAL22LV10-7LJI ispGAL22LV10-7LKI ISPGAL22LV10-10LJI ispGAL22LV10-10LKI ispGAL22LV10-15LJI ispGAL22LV10-15LKI Package 28-Lead PLCC 28-Lead SSOP 28-Lead PLCC 28-Lead SSOP 28-Lead PLCC 28-Lead SSOP Part Number Description XXXXXXXX _ XX X XX ispGAL22LV10 Device Name Grade Blank = Commercial I = Industrial Speed (ns) L = Low Power Power Package J = PLCC K = SSOP 2 Specifications ispGAL22LV10 Output Logic Macrocell (OLMC) The ispGAL22LV10 has a variable number of product terms per OLMC. Of the ten available OLMCs, two OLMCs have access to eight product terms (pins 17 and 27), two have ten product terms (pins 18 and 26), two have twelve product terms (pins 19 and 25), two have fourteen product terms (pins 20 and 24), and two OLMCs have sixteen product terms (pins 21 and 23). In addition to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control. The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode. This allows each output to be individually configured as either active high or active low. The ispGAL22LV10 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP). These two product terms are common to all registered OLMCs. The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted. The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted. NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output. Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen. AR D Q CLK SP Q 4 TO 1 MUX 2 TO 1 MUX ispGAL22LV10 OUTPUT LOGIC MACROCELL (OLMC) Output Logic Macrocell Configurations Each of the Macrocells of the ispGAL22LV10 has two primary functional modes: registered, and combinatorial I/O. The modes and the output polarity are set by two bits (S0 and S1), which are normally controlled by the logic compiler. Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page. REGISTERED In registered mode the output pin associated with an individual OLMC is driven by the Q output of that OLMC's D-type flip-flop. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation. The D flip-flop's /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array. NOTE: In registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic I/O, as can the combinatorial pins. COMBINATORIAL I/O In combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate. Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low). Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either "on" (dedicated output), "off" (dedicated input), or "product-term driven" (dynamic I/O). Feedback into the AND array is from the pin side of the output enable buffer. Both polarities (true and inverted) of the pin are fed back into the AND array. 3 Specifications ispGAL22LV10 Registered Mode AR AR D Q D Q CLK SP Q CLK SP Q ACTIVE LOW S0 = 0 S1 = 0 S0 = 1 S1 = 0 ACTIVE HIGH Combinatorial Mode ACTIVE LOW S0 = 0 S1 = 1 S0 = 1 S1 = 1 ACTIVE HIGH 4 Specifications ispGAL22LV10 ispGAL22LV10 Logic Diagram/JEDEC Fuse Map PLCC & SSOP Package Pinout 2 0 0000 0044 . . . 0396 4 8 12 16 20 24 28 32 36 40 ASYNCHRONOUS RESET (TO ALL REGISTERS) 8 OLMC S0 5808 S1 5809 27 0440 . . . . 0880 10 OLMC S0 5810 S1 5811 26 3 0924 . . . . . 1452 12 OLMC S0 5812 S1 5813 25 4 1496 . . . . . . 2112 14 OLMC S0 5814 S1 5815 24 5 2156 . . . . . . . 2860 16 OLMC S0 5816 S1 5817 23 6 2904 . . . . . . . 3608 16 OLMC S0 5818 S1 5819 21 7 3652 . . . . . . 4268 14 OLMC S0 5820 S1 5821 20 9 4312 . . . . . 4840 12 OLMC S0 5822 S1 5823 19 10 4884 . . . . 5324 10 OLMC S0 5824 S1 5825 18 11 5368 . . . 5720 8 OLMC S0 5826 S1 5827 17 12 5764 13 5828, 5829 ... M S B L S B SYNCHRONOUS PRESET (TO ALL REGISTERS) 16 Electronic Signature ... 5890, 5891 Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte 1 Byte 0 5 Specifications ispGAL22LV10 Absolute Maximum Ratings(1) Supply voltage VCC .................................... -0.5 to +4.6V Input and I/O voltage applied ..................... -0.5 to +5.6V Off-state output voltage applied ................ -0.5 to +4.6V Storage Temperature ................................. -65 to 150C Ambient Temperature with Power Applied ......................................... -55 to 125C 1.Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). Recommended Operating Conditions Commercial Devices: Ambient Temperature (TA) ............................... 0 to 75C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V Industrial Devices: Ambient Temperature (TA) ............................ -40 to 85C Supply voltage (VCC) with Respect to Ground ......................... +3.0 to +3.6V DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER Input Low Voltage Input or I/O High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current Input or I/O High Leakage Current 0V VIN VIL (MAX.) (Vcc-0.2)V VIN VCC Vcc VIN 5.25V IOL = MAX. Vin = VIL or VIH IOL = 500A Vin = VIL or VIH CONDITION MIN. Vss - 0.3 2.0 -- -- -- -- -- 2.4 Vcc-0.2V -- -- -- -- VCC = 3.3V VOUT = 0.5V TA= 25C -30 TYP.3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- MAX. 0.8 5.25 -150 10 2 0.4 0.2 -- -- 8 4 -8 -2 -80 UNITS V V A A mA V V V V mA mA mA mA mA VIL VIH IIL1 IIH VOL VOH IOL IOL-ISP IOH IOH-ISP IOS2 Output Low Voltage Output High Voltage IOH = MAX. Vin = VIL or VIH IOH = -100A Vin = VIL or VIH Low Level Output Current Low Level Output Current TDO High Level Output Current High Level Output Current TDO Output Short Circuit Current COMMERCIAL ICC Operating Power Supply Current VIL = 0V VIH = 3.0V Unused Inputs at VIL ftoggle = 1MHz Outputs Open -- 90 130 mA INDUSTRIAL ICC Operating Power Supply Current VIL = 0V VIH = 3.0V Unused Inputs at VIL ftoggle = 1MHz Outputs Open -- 90 160 mA 1) The leakage current is due to the internal pull-up resistor on all pins. See Input Buffer section for more information. 2) One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3) Typical values are at Vcc = 3.3V and TA = 25 C 6 Specifications ispGAL22LV10 AC Switching Characteristics Over Recommended Operating Conditions COM PARAM. TEST DESCRIPTION COND1. COM COM/IND COM/IND COM/IND -4 MIN. MAX. -5 -7 -10 -15 UNITS ns ns ns ns ns MHz MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. tpd2 tco2 tcf3 tsu th A A -- -- -- A Input or I/O to Comb. Output Clock to Output Delay Clock to Feedback Delay Setup Time, Input or Fdbk before Clk Hold Time, Input or Fdbk after Clk Maximum Clock Frequency with External Feedback, 1/(tsu + tco) Maximum Clock Frequency with Internal Feedback, 1/(tsu + tcf) Maximum Clock Frequency with No Feedback Clock Pulse Duration, High Clock Pulse Duration, Low Input or I/O to Output Enabled Input or I/O to Output Disabled Input or I/O to Asynch. Reset of Reg. Asynchronous Reset Pulse Duration Asynch. Reset to Clk Recovery Time Synch. Preset to Clk Recovery Time 1 1 -- 3 0 167 4 3 2.5 -- -- -- 1 1 -- 3.5 0 143 5 3.5 2.5 -- -- -- 1 1 -- 5 0 100 7.5 5 2.5 -- -- -- 1 1 -- 7 0 74 10 6.5 2.5 -- -- -- 1 -- -- 10 0 55.5 15 8 2.5 -- -- -- fmax4 A A 182 250 -- -- 166 200 -- -- 133 166 -- -- 105 111 -- -- 80 83.3 -- -- MHz MHz twh4 twl4 ten tdis tar tarw tarr tspr -- -- B C A -- -- -- 2 2 1 1 1 4.5 3.5 3.5 -- -- 5 5 4.5 -- -- -- 2.5 2.5 1 1 1 5.5 4 4 -- -- 6 6 5.5 -- -- -- 3 3 1 1 1 7 5 5 -- -- 7.5 7.5 9 -- -- -- 4 4 1 1 1 8 8 10 -- -- 10 10 13 -- -- -- 6 6 -- -- -- 15 10 10 -- -- 15 15 20 -- -- -- ns ns ns ns ns ns ns ns 1) Refer to Switching Test Conditions section. 2) Minimum values for tpd and tco are not 100% tested but established by characterization. 3) Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 4) Refer to fmax Descriptions section. Characterized but not 100% tested. Note: Maximum clock input rise and fall time between 10% to 90% of Vout = 2ns. Capacitance (TA = 25C, f = 1.0 MHz) SYMBOL CI CI/O PARAMETER Input Capacitance I/O Capacitance TYPICAL 4 5 UNITS pF pF TEST CONDITIONS VCC = 3.3V, VI = 0V VCC = 3.3V, VI/O = 0V 7 Specifications ispGAL22LV10 Switching Waveforms INPUT or I/O FEEDBACK VALID INPUT INPUT or I/O FEEDBACK VALID INPUT tpd COMBINATORIAL OUTPUT ts u CLK th tc o Combinatorial Output REGISTERED OUTPUT 1/ fm a x (external fdbk) Registered Output INPUT or I/O FEEDBACK tdis OUTPUT ten CLK 1/ fm a x (int ern al fd bk ) Input or I/O to Output Enable/Disable REGISTERED FEEDBACK tc f tsu tw h CLK 1/ tw l fmax with Feedback fm a x (w/o fdbk) Clock Width INPUT or I/O FEEDBACK DRIVING SP CLK INPUT or I/O FEEDBACK DRIVING AR tsu th tspr CLK tarw tco REGISTERED OUTPUT REGISTERED OUTPUT tarr tar Synchronous Preset Asynchronous Reset 8 Specifications ispGAL22LV10 fmax Descriptions CL K CLK LOGIC ARR AY R EG I S T E R LOGIC ARRAY REGISTER ts u tc o tcf tpd fmax with External Feedback 1/(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco. CLK fmax with Internal Feedback 1/(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu). The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. LOGIC ARRAY REGISTER tsu + th fmax with No Feedback Note: fmax with no feedback may be less than 1/twh + twl. This is to allow for a clock duty cycle of other than 50%. Switching Test Conditions Input Pulse Levels Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load Output Load Conditions (see figure) Test Condition A B C High Z to Active High at 1.9V High Z to Active Low at 1.0V Active High to High Z at 1.9V Active Low to High Z at 1.0V R1 50 50 50 50 50 CL 35pF 35pF 35pF 35pF 35pF GND to 3.0V 1.5ns 10% - 90% 1.5V 1.5V See Figure TEST POINT R1 +1.45V FROM OUTPUT (O/Q) UNDER TEST Z0 = 50, CL = 35pF* *CL includes test fixture and probe capacitance. 9 Specifications ispGAL22LV10 Electronic Signature An electronic signature (ES) is provided in every ispGAL22LV10 device. It contains 64 bits of reprogrammable memory that can contain user-defined data. Some uses include user ID codes, revision numbers, or inventory control. The signature data is always available to the user independent of the state of the security cell. The electronic signature is an additional feature not present in other manufacturers' 22V10 devices. To use the extra feature of the user-programmable electronic signature it is necessary to choose a Lattice Semiconductor 22V10 device type when compiling a set of logic equations. In addition, many device programmers have two separate selections for the device, typically an ispGAL22LV10 and a ispGAL22LV10-UES (UES = User Electronic Signature) or ispGAL22LV10-ES. This allows users to maintain compatibility with existing 22V10 designs, while still having the option to use the GAL device's extra feature. The JEDEC map for the ispGAL22LV10 contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses. However, the ispGAL22LV10 device can still be programmed with a standard 22V10 JEDEC map (5828 fuses) with any qualified device programmer. All necessary programming is done via four TTL level logic interface signals. These four signals are fed into the on-chip programming circuitry where a state machine controls the programming. The interface signals are Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK) and Test Mode Select (TMS) control. For details on the operation of the internal state machine and programming of ispGAL22LV10 devices please refer to the ISP Architecture and Programming section in this Data Book. Output Register Preload When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brownouts, etc.). To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. Then the machine can be sequenced and the outputs tested for correct next state conditions. The ispGAL22LV10 device includes circuitry that allows each registered output to be synchronously set either high or low. Thus, any present state condition can be forced for test sequencing. If necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically. Security Cell A security cell is provided in every ispGAL22LV10 device to prevent unauthorized copying of the array patterns. Once programmed, this cell prevents further read access to the functional bits in the device. This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed. The Electronic Signature is always available to the user, regardless of the state of this control cell. Input Buffers ispGAL22LV10 devices are designed with TTL level compatible input buffers. These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices. All input and I/O pins also have built-in active pull-ups. As a result, floating inputs will float to a TTL high (logic 1). However, Lattice Semiconductor recommends that all unused inputs and tri-stated I/O pins be connected to an adjacent active input, Vcc, or ground. Doing so will tend to improve noise immunity and reduce Icc for the device. (See equivalent input and I/O schematics on the following page.) Typical Input Current 0.00 Latch-Up Protection ispGAL22LV10 devices are designed with an on-board charge pump to negatively bias the substrate. The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch. Device Programming Input Current (A) The ispGAL22LV10 device uses a standard 22V10 JEDEC fusemap file to describe the device programming information. Any third party logic compiler can produce the JEDEC file for this device. -10.00 -20.00 -30.00 -40.00 -50.00 0.00 In-System Programmability The ispGAL22LV10 device features In-System Programmable technology. By integrating all the high voltage programming circuitry on-chip, programming can be accomplished by simply shifting data into the device. Once the function is programmed, the non-volatile E2CMOS cells will not lose the pattern even when the power is turned off. 1.00 2.00 3.00 4.00 Input Voltage (Volts) 10 Specifications ispGAL22LV10 Power-Up Reset Vcc Vcc (min.) tsu CLK twl tpr INTERNAL REGISTER Q - OUTPUT Internal Register Reset to Logic "0" ACTIVE LOW OUTPUT REGISTER Device Pin Reset to Logic "1" ACTIVE HIGH OUTPUT REGISTER Device Pin Reset to Logic "0" Circuitry within the ispGAL22LV10 provides a reset signal to all registers during power-up. All internal registers will have their Q outputs set low after a specified time (tpr, 1s MAX). As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins. This feature can greatly simplify state machine design by providing a known state on power-up. The timing diagram for power-up is shown above. Because of the asynchronous nature of system power- up, some conditions must be met to provide a valid power-up reset of the ispGAL22LV10. First, the Vcc rise must be monotonic. Second, the clock input must be at static TTL level as shown in the diagram during power up. The registers will reset within a maximum of tpr time. As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. The clock must also meet the minimum pulse width requirements. Input/Output Equivalent Schematics PIN Feedback (Vref = Vcc) PIN Vcc Active Pull-up Circuit Active Pull-up Circuit Vcc ESD Protection Circuit Vref Vcc Tri-State Control Vcc Vref (Vref = Vcc) PIN Data Output PIN ESD Protection Circuit Feedback (To Input Buffer) Input Output 11 Specifications ispGAL22LV10 ispGAL22LV10: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc 1.2 1.15 1.03 Normalized Tco vs Vcc 1.2 Normalized Tsu vs Vcc Normalized Tco Normalized Tsu Normalized Tpd 1.1 1.05 1 0.95 0.9 0.85 3 3.15 3.3 RISE FALL 1.02 1.1 1.01 1 0.99 0.98 0.97 RISE FALL 1 RISE FALL 0.9 0.8 3 3.15 3.3 3.45 3.6 3 3.15 3.3 3.45 3.6 3.45 3.6 Supply Voltage (V) Supply Voltage (V) Supply Voltage (V) Normalized Tpd vs Temp 1.2 1.15 Normalized Tco vs Temp 1.2 1.15 Normalized Tsu vs Temp Normalized Tpd Normalized Tco Normalized Tsu RISE FALL 1.1 1.1 RISE FALL 1.1 1.05 1 0.95 0.9 RISE FALL 1.05 1 1 0.95 0.9 -55 -25 0 25 50 75 100 125 0.9 -55 -25 0 25 50 75 100 125 0.85 -55 -25 0 25 50 75 1 00 1 25 Temperature (deg. C) Temperature (deg. C) Temperature (deg. C) Delta Tpd vs # of Outputs Switching 0 0 Delta Tco vs # of Outputs Switching Delta Tpd (ns) Delta Tco (ns) -0.1 -0.1 -0.2 -0.2 -0.3 RISE FALL -0.3 RISE FALL -0.4 1 2 3 4 5 6 7 8 9 10 -0.4 1 2 3 4 5 6 7 8 9 10 Number of Outputs Switching Delta Tpd vs Output Loading 16 16 12 Number of Outputs Switching Delta Tco vs Output Loading 12 Delta Tpd (ns) Delta Tco (ns) RISE FALL 8 8 4 0 -4 4 RISE FALL 0 -4 0 50 100 150 200 250 3 00 0 50 100 150 200 250 3 00 Output Loading (pF) Output Loading (pF) 12 Specifications ispGAL22LV10 ispGAL22LV10: Typical AC and DC Characteristic Diagrams Vol vs Iol 1 3 2.9 0.8 2.8 2.7 3 Voh vs Ioh 3.05 Voh vs Ioh Voh (V) Vol (V) 0.6 2.6 2.5 2.4 2.3 Voh (V) 0 5 10 15 20 2.95 0.4 2.9 0.2 2.2 2.1 2.85 0 0 5 10 15 20 25 30 35 2 2.8 0.00 1.00 2.00 3.00 4.00 5.00 Iol (mA) Normalized Icc vs Vcc 1.15 1.2 Ioh (mA) Normalized Icc vs Temp 1.3 1.25 Ioh (mA) Normalized Icc vs Freq 1.1 Normalized Icc Normalized Icc Normalized Icc -25 0 25 50 88 100 125 1.1 1.2 1.15 1.1 1.05 1.05 1 1 0.95 0.9 0.9 3 3.15 3.3 3.45 3.6 0.8 -55 1 1 15 25 50 75 1 00 Supply Voltage (V) Delta Icc vs Vin (1 input) 10 9 8 10 20 0 Temperature (deg. C) Input Clamp (Vik vs Iik) Frequency (MHz) Delta Icc (mA) 7 6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Iik (mA) 30 40 50 60 -2.9 -2.3 -1.7 -1.1 -0.5 0 Vin (V) Vik (V) 13 |
Price & Availability of ISPGAL22LV10-10LJ
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |